FPGA Programming File Types

Hi, I'm a sw engineer, know little about FPGA programming. Recently, I need to program the FPGA for my project. My project has Xilinx FPGA Vertex-4 and associated XCF08 PROM. I looked into the FPGA project folder, I saw there are two files, one is bit file, another is mcs file. I don't know which is for what. Can you advise?

The bit file is binary configuration data file containing header information that does not need to be downloaded to the FPGA. It is used to program FPGA devices from iMPACT with a programming cable.

The mcs file is ASCII PROM file formats containing address and checksum information in addition to configuration data. It is used mainly for device programmers and iMPACT to program the PROM device.

Thank you, lzmind, for the explanation of the file types.
I programmed the mcs file to the PROM on my target board. When the FPGA is configured as Master Serial mode, (M2 = 0, M1 = 0, M0 = 0), the loading of the code to configure the FPGA was successful, but it takes 1-2 seconds from my observation. That configuration time does not meet the requirement of the project. So I need to configure it to SelectMap mode. I have verified that the hardware connections are right, D7-D0 are connected and other control signals are connected according to Figure 2-12 Single Device Master SelectMap Configuration shown in ug071 from Xilinx. I set M2 = 0, M1 = 1, M0 = 1, however, the configuration process was failed to complete. I measured the CCLK pin and found it was always clocking. Please advise what could be wrong.

From your description, the only difference between the two modes are the serial data line and the parallel data bus. As you have proved that the D7-D0 connections are fine, we may focus on the software part from the hardware consideration.
The PROM XCFxxP has a customer controlled bits register, DATA-CCB[15:0], it controls the following PROM options:
serial or parallel data output mode and configuration clock source. The erased state for the DATA-CCB register causes the PROM to default to the slave clock and serial data output settings, corresponding to the FPGA Master Serial configuration mode. If the XCFxxP PROM is not intended to configure the FPGA in Master Serial mode, then this register is required to be programmed. Therefore, for SelectMap mode, DATA-CCB[2:1] => Serial or parallel data output mode
- 11 = Serial (1-bit) data output
- 00 = Parallel (8-bit) data output.
This is done by checking the Parallel Mode in the PROM Specific Properties section in the Device Programming Properties dialog before performing programming.

Let me know if that helps.

Hi lzmind, that was it, you are really great and saved me. I asked my FPGA colleagues for trouble shooting, they were not able to identify the cause. You are the man!